1. Field of the Invention
Example embodiments of the present invention relate generally to voltage glitch detection circuits and methods thereof, and more particularly to voltage glitch detection circuits included within integrates circuits and methods thereof.
2. Description of Related Art
An integrated circuit (IC) card, which may be alternatively referred to as a “smart card”, may be embodied as a credit-card sized plastic card with an embedded semiconductor chip. The IC card may achieve higher data integrity than conventional magnetic stripe cards. Also, the IC card may be capable of higher security protocols to protect data (e.g., additional encryption, etc.).
Data stored within an IC card may be retained, but the stored data may be vulnerable to an attacker during data transfer. For example, if an attacker directly monitors signals in the IC card to ascertain data stored therein, the monitored data may be “leaked” to the attacker.
Therefore, the IC card may include detectors to detect abnormal conditions (e.g., abnormal voltage, frequency, temperature, glitches, light exposure, etc.). If one or more of the detectors detects an abnormal condition and outputs a detection signal indicating the detected abnormal condition, all circuits including a central processing unit (CPU) installed within the IC card may be reset. Accordingly, the IC card may protect data from loss, destruction and/or variation caused by external attack under certain circumstances.
FIG. 1 illustrates a conventional IC card 10. Referring to FIG. 1, the IC card 10 may include a memory array 12, a row decoder 14, a column decoder 16, a sense amplifier 18, an output buffer 20 and a capacitor 22.
Referring to FIG. 1, the memory array 12 may include a plurality of non-volatile memory cells, for example, Electrically Erasable Programmable Read Only Memory (EEPROM) cells and/or flash memory cells. The row decoder 14 and the column decoder 16, respectively, may assign a region of the memory array 12, where data may either be written to or read from, based on a row address XADD and a column address YADD output from a control circuit (not shown).
Referring to FIG. 1, the sense amplifier 18 may amplify a voltage output from the memory array 12 and may output data set to a first logic level (e.g., a higher logic level or logic “1”) or a second logic level (e.g., a lower logic level or logic “0”) based on a logic level (e.g., “0”, “1”, etc.) of the data stored in the region assigned by the row decoder 14 and the column decoder 16. The output buffer 20 may latch the data output from the sense amplifier 18 and may output stable data.
Referring to FIG. 1, the capacitor 22 may be connected to an internal power source VDD and a ground voltage VSS of the sense amplifier 18 to protect against potential instability of the internal power source VDD and/or a “power attack” (e.g., an attempt made by an attacker to extract data from the memory cell array 12 without authorization).
However, if a power attack exceeding a limit (e.g., a current or voltage limit) of the capacitor 22 is attempted by an attacker, (e.g., an attacker causes an intentional glitch or power spike in the internal power source VDD), the sense amplifier 18 may fail to properly read the data stored in the memory array 12. Thus, a read failure may occur in the sense amplifier 18.